The present invention relates to a semiconductor design technology; and, more particularly, to a power-up signal generator of a semiconductor device.
Generally, a semiconductor device does not operate in response to an external power voltage VDD immediately after it is input therein, but operates after the input external power voltage VDD rises to a predetermined voltage level. By reason of this, most semiconductor devices should have a power-up signal generator.
In the case where an internal circuit operates after the external power voltage VDD is applied to the semiconductor device and before the external power voltage VDD reaches a predetermined voltage level, the semiconductor device can be destroyed due to the latch-up. The power-up signal generating unit outputs, for example, a power-up signal in a logic low level until the external power voltage VDD reaches a predetermined voltage level after being input, and outputs the power-up signal in a logic high level when the external power voltage VDD is stabilized over the predetermined voltage level. The internal circuit performs the stable operation in response to the power-up signal.
On the other hand, a semiconductor device, such as a DRAM, has internal power voltages which are required by each of its internal circuits. For example, the internal power voltage may be a core voltage VCORE or a pumping voltage VPP. For the core voltage VCORE and the pumping voltage VPP, it is necessary to have the individual power-up signals. A final power-up signal is produced by summing up the power-up signals which are individually created for the individual internal voltages. In this case, the semiconductor device can produce the power-up signal by considering not only the external power voltage VDD but also the states of the internal power voltages. As a result, the stability of the semiconductor device considering the external power voltage VDD and the internal power voltage may be improved, as compared with that considering only the external power voltage VDD.
FIG. 1 is a block diagram illustrating conventional internal voltage generating units and power-up signal generating units. In FIG. 1, a stabilization power-up signal generating unit 100 to which an external power voltage VDD is input produces a stabilization power-up signal PWRUP_T. A precharge power-up signal generating unit 110 to which the external power voltage VDD is input produces a precharge power-up signal PWRUP_PRE and an external voltage power-up signal generating unit 120 to which the external power voltage VDD is input produces an external voltage power-up signal PWRUP_VDD. A pumping voltage generating unit 130 to which the precharge power-up signal PWRUP_PRE is input produces a pumping voltage VPP and the pumping voltage generating unit 130 is turned off in response to a pumping voltage off signal TVPPOFF at the time of test. A core voltage generating unit 140 to which the precharge power-up signal PWRUP_PRE is input produces a core voltage VCORE and the core voltage generating unit 140 is turned off in response to a core voltage off signal TVCOREOFF at the time of test. A pumping voltage power-up signal generating unit 150 receives the pumping voltage VPP and produces a pumping voltage power-up signal PWRUP_VPP. A core voltage power-up signal generating unit 160 receives the core voltage VCORE and produces a core voltage power-up signal PWRUP_VCORE. A final power-up signal generating unit 170 receives the external voltage power-up signal PWRUP_VDD, the stabilization power-up signal PWRUP_T, the pumping voltage power-up signal PWRUP_VPP and the core voltage power-up signal PWRUP_VCORE and produces a final power-up signal PWRUP.
If the external power voltage VDD is input and increasingly rises, the stabilization power-up signal PWRUP_T generated in the stabilization power-up signal generating unit 100 is input into the final power-up signal generating unit 170. The stabilization power-up signal PWRUP_T, as a signal which is input into the final power-up signal generating unit 170 faster than the external voltage power-up signal PWRUP_VDD, prevents the final power-up signal PWRUP from being reset although the external voltage power-up signal PWRUP_VDD is turned off. Thereafter, if the voltage level of the external power voltage VDD is able to provide the internal voltage VPP and VCORE, the precharge power-up signal generating unit 110 produces the precharge power-up signal PWRUP_PRE. The pumping voltage generation unit 130 and the core voltage generating unit 140 receives this precharge power-up signal PWRUP_PRE and generate the pumping voltage VPP and the core voltage VCORE, respectively.
If the external power voltage VDD gets to a voltage level enough to stably operate the internal circuits, the external voltage power-up signal generating unit 120 produces the external voltage power-up signal PWRUP_VDD and inputs it to the final power-up signal generating unit 170. Thereafter, if the pumping voltage power-up signal generating unit 150 and the core voltage power-up signal generating unit 160, each of which receives the pumping voltage VPP and the core voltage VCORE, also get to a voltage level enough to stably operate the internal circuits, respectively, the pumping voltage power-up signal generating unit 160 produces the pumping voltage power-up signal PWRUP_VPP and the core voltage power-up signal generating unit 160 produces the core voltage power-up signal PWRUP_VCORE.
The final power-up signal generating unit 170, which receives these power-up signals, produces the final power-up signal PWRUP after confirming that the stable voltage levels are secured for the circuit operation.
FIG. 2 is a circuit diagram illustrating the power-up signal generating unit for the external power voltage in FIG. 1. Referring to FIG. 2, the external voltage power-up signal generating unit 120 includes a voltage divider 200, NMOS transistors N21 and N22, PMOS transistor P21 and a driver 210. The voltage divider 200 includes resistors R21 and R22, which are connected in series between a power supply terminal to receive the external power voltage and a ground voltage terminal VSS, for distributing a divided voltage. The NMOS transistor N21 has a gate and a source which are commonly connected to node “A” between two resistors R21 and R22 and the NMOS transistor N21 controls a voltage level which is applied to the NMOS transistor N22. The PMOS transistor P21 is disposed between the power supply terminal and the ground voltage terminal VSS and has a gate which is connected to the ground voltage terminal VSS. The NMOS transistor N22 is disposed between the PMOS transistor P21 and the ground voltage terminal VSS and has a gate which is connected to node “A.” The driver 210, which receives an output signal DET produced by the PMOS transistor P21 and the NMOS transistor N22, drives the external voltage power-up signal PWRUP_VDD.
The driver 210 can include a PMOS transistor P22, which is formed between the power supply terminal and the ground voltage terminal VSS and has a gate to which the output signal DET is applied, and an NMOS transistor N23, which is formed between the PMOS transistor P22 and the ground voltage terminal VSS and has a gate to which the output signal DET is applied.
The external voltage power-up signal PWRUP_VDD is output in a logic low level when the NMOS transistor N23 of the driver 210 is turned on by the output signal DET which is output in a logic high level by the PMOS transistor P21. As the external power voltage VDD gradually increases, a divided voltage is produced at node “A” of the voltage divider 200 to divide the external power voltage VDD. The more the external power voltage VDD increases, the higher the divided voltage at node “A” becomes. This increased divided voltage turns on the NMOS transistor N22. Accordingly, the output signal DET input to the driver 210 turns on the PMOS transistor P22 and then the external voltage power-up signal PWRUP_VDD goes from a logic low level to a logic high level. That is, the external power supply power-up signal PWRUP_VDD transitions from a logic low level to a logic high level at the point of time when the external power voltage VDD has a desired voltage level.
FIG. 3 is a circuit diagram illustrating the power-up signal generating unit for a pumping voltage in FIG. 1. The pumping voltage power-up signal generating unit 150 has a configuration which is similar to the external voltage power-up signal generating unit 120 of FIG. 2. However, instead of the power supply voltage VDD applied to the voltage divider 200 of FIG. 2, the pumping voltage VPP generated by the pumping voltage generating unit 130 in FIG. 1 is applied to the pumping voltage power-up signal generating unit 150.
Referring to FIG. 3, the pumping voltage power-up signal generating unit 150 includes a voltage divider 300, NMOS transistors N31 and N32, PMOS transistor P31 and a driver 310. The voltage divider 300 includes resistors R31 and R32, which are connected in series between a power supply terminal to receive the pumping voltage VPP and a ground voltage terminal VSS, for distributing a divided voltage. The NMOS transistor N31 has a gate and a source which are commonly connected to node “B” between two resistors R31 and R32 and the NMOS transistor N31 controls a voltage level which is applied to the NMOS transistor N32. The PMOS transistor P31 is disposed between the power supply terminal and the ground voltage terminal VSS and has a gate which is connected to the ground voltage terminal VSS. The NMOS transistor N32 is disposed between the PMOS transistor P31 and the ground voltage terminal VSS and has a gate which is connected to node “B.” The driver 310, which receives an output signal DET produced by the PMOS transistor P31 and the NMOS transistor N32, drives the pumping voltage power-up signal PWRUP_VPP.
The driver 310 can include a PMOS transistor P32, which is formed between the power supply terminal and the ground voltage terminal VSS and has a gate to which the output signal DET is applied, and an NMOS transistor N33, which is formed between the PMOS transistor P32 and the ground voltage terminal VSS and has a gate to which the output signal DET is applied.
The pumping voltage power-up signal PWRUP_VPP is output in a logic low level when the NMOS transistor N33 of the driver 310 is turned on by the output signal DET which is output in a logic high level by the PMOS transistor P31. As the pumping voltage VPP gradually increases, the divided voltage is produced at node “B” of the voltage divider 300 to divide the pumping voltage VPP. The more the pumping voltage VPP increases, the higher the divided voltage at node “B” becomes. This increased divided voltage turns on the NMOS transistor N32. Accordingly, the output signal DET input to the driver 310 turns on the PMOS transistor P32 and then the pumping voltage power-up signal PWRUP_VPP goes from a logic low level to a logic high level.
That is, the pumping power supply power-up signal PWRUP_VPP transitions from a logic low level to a logic high level at the point of time when the pumping power voltage VPP has a desired voltage level.
FIG. 4 is a circuit diagram illustrating the power-up signal generating unit for a core voltage in FIG. 1. The core voltage power-up signal generating unit 160 has a configuration which is similar to the external voltage power-up signal generating unit 120 of FIG. 2. However, instead of the power supply voltage VDD applied to the voltage divider 200 of FIG. 2, the core voltage VCORE generated by the core voltage generating unit 140 in FIG. 1 is applied to the core voltage power-up signal generating unit 160.
Referring to FIG. 4, the core voltage power-up signal generating unit 160 includes a voltage divider 400, NMOS transistors N41 and N42, PMOS transistor P41 and a driver 410. The voltage divider 400 includes resistors R41 and R42, which are in series connected between a power supply terminal to receive the core voltage and a ground voltage terminal VSS, for distributing a divided voltage. The NMOS transistor N41 has a gate and a source which are commonly connected to node “C” between two resistors R41 and R42 and the NMOS transistor N41 controls a voltage level which is applied to the NMOS transistor N42. The PMOS transistor P41 is disposed between the power supply terminal and the ground voltage terminal VSS and has a gate which is connected to the ground voltage terminal VSS. The NMOS transistor N42 is disposed between the PMOS transistor P41 and the ground voltage terminal VSS and has a gate which is connected to node “C.” The driver 410, which receives an output signal DET produced by the PMOS transistor P41 and the NMOS transistor N42, drives the core voltage power-up signal PWRUP_VCORE.
The driver 410 can include a PMOS transistor P42, which is formed between the power supply terminal and the ground voltage terminal VSS and has a gate to which the output signal DET is applied, and an NMOS transistor N43, which is formed between the PMOS transistor P42 and the ground voltage terminal VSS and has a gate to which the output signal DET is applied.
The core voltage power-up signal PWRUP_VDD is output in a logic low level when the NMOS transistor N43 of the driver 410 is turned on by the output signal DET which is output in a logic high level by the PMOS transistor P41. As the core voltage VCORE gradually increases, the divided voltage is produced at node “C” of the voltage divider 400 to divide the core voltage VCORE. The more the core voltage VCORE increases, the higher the divided voltage at node “C” becomes. This increased divided voltage turns on the NMOS transistor N42. Accordingly, the output signal DET input to the driver 410 turns on the PMOS transistor P42 and then the core voltage power-up signal PWRUP_VCORE goes from a logic low level to a logic high level. That is, the core voltage power-up signal PWRUP_VCORE transitions from a logic low level to a logic high level at the point of time when the core voltage VCORE has a desired voltage level.
FIG. 5 is a circuit diagram illustrating a final power-up signal generating unit in FIG. 1. Referring to FIG. 1, the final power-up signal generating unit 170 includes a PMOS transistor P51, an NMOS transistor N51, a latch unit 500, a NAND gate NAND51 and an inverter INV53. The PMOS transistor P51 is disposed between the power supply terminal to receive the external power voltage VDD and node “D” and has a gate to which the stabilization power-up signal PWRUP_T is applied. The NMOS transistor N51 is disposed between node “D” and the ground voltage terminal and has a gate to which the external voltage power-up signal PWRUP_VDD is applied. The latch unit 500, having two inverters INV51 and INV52, receives the voltage on node “D” and temporarily stores the latched voltage. The NAND gate NAND51 receives an output signal of the latch unit 500, the pumping voltage power-up signal PWRUP_VPP and the core voltage power-up signal PWRUP_VCORE and performs the NAND operation of the received signals. The inverter INV53 inverts an output signal of the NAND gate NAND51 to output the final power-up signal PWRUP.
The input terminal of the latch unit 500 is in a logic high level by turning on the PMOS transistor P51 in response to the stabilization power-up signal PWRUP_T in a logic low level before the external voltage power-up signal PWRUP_VDD is enabled. At this time, the final power-up signal PWRUP is output in a logic low level. Thereafter, when the external voltage power-up signal PWRUP_VDD is in a logic high level, the input terminal of the latch unit 500 is in a logic low level. Since the power-up signal PWRUP_T in a logic high level turns off the PMOS transistor P51, the latched value in the latch unit 500 is maintained even if the external voltage power-up signal PWRUP_VDD goes down to a low voltage due to the unstable external power voltage VDD and then does not turn on the NMOS transistor N51.
Thereafter, the core voltage power-up signal PWRUP_VCORE and the pumping voltage power-up signal PWRUP_VPP transition to a logic high level and the final power-up signal PWRUP then transits to a logic high level. As described above, the conventional final power-up signal generating unit 170 detects the voltage levels of the external power voltage VDD, the core voltage VCORE and the pumping voltage VPP and outputs the final power-up signal PWRUP after confirming each of the individual power-up signals. However, the above-mentioned method has, in a test mode, a problem in the case where the pumping voltage off signal TVPPOFF for turning off the pumping voltage generating unit 130 of FIG. 1 is enabled or the core voltage off signal TVCOREOFF for turning off the core voltage generating unit 140 is enabled. In other words, if one of the pumping voltage off signal TVPPOFF and the core voltage off signal TVCOREOFF is enabled, one of the pumping voltage generating unit 130 and the core voltage generating unit 140 is turned off. Therefore, each of the power-up signal generating units, which respectively receive the core voltage VCORE and the pumping voltage VPP; cannot produce the desired power-up signal. As a result, the case where the final power-up signal PWRUP is disabled can be generated. This can give rise to the serious problem of causing the mode register to set (MRS) and other circuits to reset.